The present invention relates to techniques and assemblies for making electrical interconnections to contact elements on a semiconductor device during a temporary connection to the device, i.e. in test and/or burn-in procedures.
Rapid advances in microelectronic devices are continuously demanding finer pitch connections between electronic chip carriers and printed circuit boards (on the order of a few hundred micrometer pitch or less). This demand as well as the demand for low cost electronic packages have led to the increased use of surface mount technology (SMT) over the conventional plated-through-hole (PTH) technology in the recent years. At present, more than two thirds of integrated circuits (IC) including both memory and logic devices are assembled by SMT. SMT packages commonly found in a printed circuit board (PCB) assembly are leaded chip carriers such as small outline integrated circuits (SOIC), plastic leaded chip carrier (PLCC), quad flat pack (QFP), thin small outline package (TSOP), or tape carrier package (TCP). These leaded chip carriers depend upon a perimeter connection between an IC package and a PCB. The perimeter connection scheme of SMT packages has reached its limitation in terms of connection pitch and I/O capability, particularly for high performance IC""s.
To relieve the limitations of perimeter connections and thereby to increase the packaging density, area array connection and packaging schemes have become popular. Some of the area array packages developed for SMT include the ball grid array (BGA) package, solder column grid array (SCGA), direct chip attach (DCA) to PCB by flip chip connection, tape ball grid array (TBGA), and chip scale packages (CSP). A typical BGA array has a pitch in the 40-50 mil range, while for the CSP arrays the pitch may go down to 15 mils. Among them, BGA is currently the most popular one, where solder balls connect a module carrying an IC to a PCB. This technology is an extension of the controlled collapse chip connection (C4) scheme originally developed for solder bump connection of multiple chips to a ceramic substrate.
The IC on the module can be connected to the module in several ways as taught by Mulles et al., U.S. Pat. No. 5,241,133; Massingill, U.S. Pat. No. 5,420,460; and Marrs et al., U.S. Pat. No. 5,355,283 among others. Ceramic or organic module substrates can be employed depending on the performance, weight and other requirements. The common feature, however, is that the connection between the IC carrier and the next level PCB is accomplished by an array of solder balls which are attached to the module by a solder alloy with a lower melting temperature.
Semiconductor components, such as bare dice, or chip scale and BGA packages, must be tested prior to shipment by semiconductor manufacturers. Since these components are relatively small and fragile, carriers have been developed for handling the components for testing. The carriers permit electrical connections to be made between external contacts on the components, and testing equipment such as burn-in boards. On bare dice, the external contacts typically comprise planar or bumped bond pads. On chip scale packages, the external contacts typically comprise solder balls in a dense array, such as a ball grid array, or a fine ball grid array.
A significant problem associated with BGA modules is the difficulty associated with testing and xe2x80x9cburning-inxe2x80x9d the assembly after a silicon die has been assembled on them. Although the die may have been tested prior to BGA assembly, the devices and circuitry have to be retested because of the additional temperature and handling exposures involved in the BGA and other assembly procedures. This poses a problem because the only way to access the chip devices is through the BGA balls. Establishing reliable contact for testing and burn-in has been difficult when using prior art testing and burn-in devices that are often designed for engaging pin grid array modules. Even if alternate means could be designed to contact the BGA balls, these would most likely require mechanical pressure of pads or xe2x80x9cbed-of-nailsxe2x80x9d type pin arrays on a test board to be pressed against the solder balls. These approaches are often unreliable due to the softness of the BGA balls and the tenacious oxide present on their surface. Additionally, the application of pressure during the testing can deform or even dislodge the BGA balls causing yield loss.
What is needed is an interconnect component that includes contacts that make a temporary non-damaging electrical connection with the external BGA contacts. The interconnect component should provide power, ground and signal paths to the BGA component. A biasing force for biasing the component against the interconnect must be provided that will achieve viable electrical connection, but without damaging the delicate solder ball surfaces.
The present invention provides an interconnection device for temporary connection of a first electronic system to a second electronic system having a support substrate that includes an ordered array of conductive solder pads. A plurality of coil signal contacts are mounted to the conductive solder pads. Each one of the coil signal contacts comprises a central longitudinal axis, a top turn and a bottom turn that are arranged in spaced relation to one another. In this way, the bottom turn of one of the plurality of coil signal contacts is fastened to each of the conductive pads such that the top turns are spaced away from the support substrate.
In one alternative embodiment of the invention, an interconnection device for temporary connection of a first electronic system to a second electronic system is provided having a plurality of dual coil signal contacts where each one of the dual coil signal contacts comprises a tail connecting a top coil having a contact turn and a bottom coil having a contact turn. Each of the dual coil contacts is arranged such that the top coil and the bottom coil project outwardly and away from one another. The dual coil contacts are mounted within a support substrate having a top carrier including a first plurality of through-holes, a bottom carrier including a second plurality of through-holes, and a lock-plate including a third plurality of through-holes. The top carrier and the bottom carrier are joined to one another such that the first plurality of through-holes and the second plurality of through-holes are substantially coaxially aligned, and the lock-plate is slideably sandwiched between the top carrier and the bottom carrier. In this way, the lock-plate may slide between (i) a first position wherein the first plurality of through-holes, the second plurality of through-holes, and the third plurality of through-holes are coaxially aligned whereby one of the dual coil signal contacts may be slid through the through-holes so as to be mounted to the substrate; and (ii) a second position wherein only the first plurality of through-holes and the second plurality of through-holes are coaxially aligned and the tail of the dual coil contact is locked within the third through-hole.
In another alternative embodiment of the invention, an interconnection device for temporary connection of a first electronic system to a second electronic system is provided including a plurality of dual coil signal contacts. Each of the of dual coil signal contacts comprises a top coil having a contact turn, a bottom coil having a contact turn, and a central lock-turn that has a substantially larger diameter than the contact turns. Each of the dual coil contacts are arranged such that the top coil and the bottom coil project outwardly and away from the lock-turn. The dual coil signal contacts are mounted within a support substrate having a top carrier including a plurality of through-holes and a bottom carrier including a plurality of countersunk through-holes. The countersunk through-holes are defined by an annular ledge disposed about a central opening of the through-hole. When a dual coil signal contact is positioned within the bottom carrier of a substrate such that its bottom coil projects outwardly from the countersunk through-hole, the central lock-turn engages the ledge and is locked in place when the top carrier and the bottom carrier are joined to one another.
An electrical connection system is also provided in which a temporary connection is made between an electronic circuit package and an electronic system. In this aspect of the invention, a semiconductor package is provided having a housing with a plurality of solder balls arranged in an array on at least one side. Each of the solder balls comprises a semispherical profile having a center top region spaced away from the housing, and a peripheral edge region that is between the center top region and the housing. An interconnection device is provided having a support substrate including an ordered array of conductive pads. Each one of the signal contacts comprises a central longitudinal axis, a top conductor and a bottom conductor that are arranged in spaced relation to one another. The top conductor is sized so as to engage the substantially semispherical solder ball along the peripheral edge region, and the bottom conductor is fastened to one of the conductive pads.